The semiconductor industry is continuously moving toward the fabrication of smaller and more complex integrated circuits with higher performance. During a typical manufacturing process, several stacked layers of dielectric materials are formed during back end of line (BEOL) fabrication. The stacked layers of dielectric materials include interconnects, contacts, and various components that electrically connect electronic components of the integrated circuit in a desired pattern. These interconnects, contacts, and other components are aligned to make the proper electrical connections. Improper alignment can result in shorts or other malfunctions in the integrated circuit. Overlay marks (sometimes referred to as alignment marks) are generally added at select locations in the stacked layers of dielectric materials to verify that each subsequent layer is properly aligned. The overlay marks are formed in adjacent stacked layers and compared to each other to verify that the adjacent layers are properly aligned. Many different types of overlay marks can be used, such a series of elongated rectangular bodies that are intended to line up with another series of elongated rectangular bodies in an adjacent layer, or a box shape in one layer that is intended to line up with a frame in an adjacent layer, or a box shape in one layer that is intended to line up with a box shape in another layer. The BEOL fabrication process can be adjusted if the overlay marks indicate that the adjacent layers are misaligned.
Overlay marks are generally formed using lithographic techniques. During lithographic processing, a photoresist layer is formed overlying one or more layers of dielectric material, where the layers of dielectric materials overlay various electronic components. Some of the electronic components include metals that can reflect light, such as copper, aluminum, or tungsten. When the overlay marks are inspected to determine alignment issues, incident light can travel through the one or more layers of dielectric materials and reflect back to a sensing device from reflective parts of the electronic components positioned underneath the overlay marks. The reflected light can shift the apparent or perceived position of the alignment marks during inspection, thereby resulting in unwanted measurement errors. A block may be formed underlying a set of overlay marks and overlying electronic components with reflective parts to minimize reflection of the light from underlying components in an unplanned and random manner. As such, the block can improve the measurement accuracy for the overlay marks during inspection. The block is a pad that is typically formed at the same time as interconnects, and is therefore formed from the same material as the interconnects. The block is generally electrically isolated by layers of dielectric material so as not to interfere or influence the operation of the integrated circuit.
In many embodiments, overburden produced during the formation of the block is removed through chemical mechanical planarization (CMP). For many block materials, the upper surface of the block is removed at a faster rate than the adjacent dielectric material. This results in the block having a dished upper surface, with the edges of the block being thicker than the center area of the block that is further from the dielectric material. As a result, some of the overlay marks may be positioned over a sloped area of the dished upper surface of the block. The sloped area of the dished upper surface of the block results in an unintended angled reflection of the light that passes through dielectric layers that overlie the sloped area. The overlay marks are inspected during metrology to determine the alignment of adjacent layers, and light is used to inspect and measure the alignment. Incident light travels through the dielectric layers during metrology, and the unintended angled reflection can result in measurement errors because the overlay marks appear to be shifted from their actual location. The dishing also changes the dielectric layer thickness overlying the block, and the varying thickness can also produce metrology errors in some cases.
Accordingly, it is desirable to provide integrated circuits and methods of manufacturing integrated circuits with little or no shift in the apparent position of overlay marks during inspection. In addition, it is desirable to provide integrated circuits and methods of manufacturing integrated circuits with reduced dishing of the block, and/or with symmetrical dishing of the block such that the appearance of an overlay mark geometric center is close to the actual location of the overlay mark geometric center. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.